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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps; serial JESD204A interface
Rev. 02 -- 4 June 2009 Objective data sheet
1. General description
The ADC1413D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1413D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V source for analog and a 1.8 V source for the output driver, it has two serial outputs, because of the two lanes of differential outputs, which are compliant with the JESD204A standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC. A set of IC configurations is also available via the binary level control pins taken, which are used at power-up. The device also includes a programmable gain amplifier with flexible input voltage range. Excellent dynamic performance is maintained from the baseband to input frequencies of 170 MHz or more, making the ADC1413D ideal for use in communications, imaging and medical applications.
2. Features
I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual channel 14-bit pipelined ADC core 3.3 V, 1.8 V single supplies Flexible input voltage range: 1 V (p-p) to 2 V (p-p) with 6 dB programmable fine gain I 2 configurable serial outputs I Compliant with JESD204A serial transmission standard I INL 1 LSB; DNL 0.5 LSB I I I I I I Input bandwidth, 600 MHz Power dissipation, 995 mW at 80 Msps SPI interface Duty cycle stabilizer High IF capability Offset binary, 2's complement, gray code
I Power-down and Sleep modes I HVQFN56 package
3. Applications
I Wireless and wired broadband communications I Spectral analysis I Portable instrumentation I Ultrasound equipment I Imaging systems
NXP Semiconductors
ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
4. Ordering information
Table 1. Ordering information Sampling frequency (Msample/s) 125 105 80 65 Package Name HVQFN56 HVQFN56 HVQFN56 HVQFN56 Description Version Type number
ADC1413D125HN/C1 ADC1413D105HN/C1 ADC1413D080HN/C1 ADC1413D065HN/C1
plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 x 8 x 0.85 mm plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 x 8 x 0.85 mm plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 x 8 x 0.85 mm plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 x 8 x 0.85 mm
ADC1413D065_080_105_125_2
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Objective data sheet
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
5. Block diagram
CFG (0 TO 3)
SCLK/DFS
SDIO/DCS
PGA
ERROR CORRECTION AND DIGITAL PROCESSING
SPI INTERFACE
CSB
SYNCP SYNCN
INAP T/H INPUT STAGE INAM 8b CLOCK INPUT STAGE & DUTY CYCLE CONTROL FRAME ASSEMBLY ADCA CORE 14-BIT PIPELINED D13 to D0 ENCODER 8b/10b A OTR SCRAMBLER A
SWING
SERIALIZER A 10b OUTPUT BUF A
CMLAP
8b
CMLAN
CLKP DLL PLL CLKM ERROR CORRECTION AND DIGITAL PROCESSING
ENCODER 8b/10b B
SCRAMBLER B
SERIALIZER B 10b OUTPUT BUF B
CMLBP
PGA
8b
8b
CMLBN
INBP T/H INPUT STAGE INBM ADCB CORE 14-BIT PIPELINED
OTR D13 to D0
SWING
CLOCK INPUT STAGE & DUTY CYCLE CONTROL
SYSTEM REFERENCE AND POWER MANAGEMENT
ADC1413D
SCRAMBLER RESET
SENSE VDDD DGND VDDA AGND
005aaa067
Fig 1.
Block diagram
ADC1413D065_080_105_125_2
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
6. Pinning information
6.1 Pinning
49 PLL_LOCK 48 SWING_1 47 SWING-0
44 SYNCN
INAP INAM VCMA REFAT REFAB AGND CLKP CLKN AGND
1 2 3 4 5 6 7 8 9
43 SYNCP 42 DGND 41 DGND 40 VDDD 39 CMLPA 38 CMLNA 37 VDDD 36 DGND 35 DGND 34 VDDD 33 CMLNB 32 CMLPB 31 VDDD 30 DGND 29 DGND DGND 28
005aaa068
54 SENSE
ADC1413D
REFBB 10 REFBT 11 VCMB 12 INBM 13 INBP 14 VDDA 15 VDDA 16 SCLK/DCS 17 SDIO/DCS 18 CSB 19 AGND 20 RESET 21 SCRAMBLER 22 CFG0 23 CFG1 24 CFG2 25 CFG3 26 VDDD 27
Transparent top view
Fig 2.
Pinning diagram
6.2 Pin description
Table 2. Symbol INAP INAM VCMA REFAT REFAB AGND CLKP CLKN AGND REFBB REFBT VCMB INBM
ADC1413D065_080_105_125_2
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Type [1] I I O O O G I I G O O O I Description channel A complementary analog input channel A analog input channel A output common voltage channel A top reference Channel A bottom reference analog ground clock input complementary clock Input analog ground channel B bottom reference channel B top reference channel B output common voltage channel B complementary analog input
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
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45 DGND
52 AGND
51 AGND
46 VDDD
56 VDDA
53 VDDA
50 VDDA
55 VREF
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Pin description ...continued Pin 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Type [1] I P P I I/O I G I I I/O I/O I/O I/O P G G G P O O P G G P O O P G G I I G P I I O P G G P I I/O P Description channel B analog input analog power supply 3.3 V analog power supply 3.3 V SPI clock / data format select SPI data IO/duty cycle stabilizer chip select bar analog ground JEDEC digital IP reset scrambler enable /disable JEDEC link configuration or OTRA JEDEC link configuration or OTRB JEDEC link configuration JEDEC link configuration digital power supply 1.8 V digital ground digital ground digital ground digital power supply 1.8 V channel B output channel B complementary output digital power supply 1.8 V digital ground digital ground digital power supply 1.8 V channel A complementary output channel A output digital power supply 1.8 V digital ground digital ground synchronization from FPGA synchronization from FPGA digital ground digital power supply 1.8 V JESD204 serial buffer programmable output swing JESD204 serial buffer programmable output swing set when internal PLL is locked analog power supply 3.3 V analog ground analog ground analog power supply 3.3 V reference programming pin voltage reference input/output analog power supply 3.3 V
Table 2. Symbol INBP VDDA VDDA SCLK/DFS SDIO/DCS CSB AGND RESET
SCRAMBLER CFG0 CFG1 CFG2 CFG3 VDDD DGND DGND DGND VDDD CMLPB CMLNB VDDD DGND DGND VDDD CMLNA CMLPA VDDD DGND DGND SYNCP SYNCN DGND VDDD SWING_0 SWING_1 PLL_LOCK VDDA AGND AGND VDDA SENSE VREF VDDA
[1]
ADC1413D065_080_105_125_2
P: power supply; G: ground; I: input; O: output; I/O: input/output.
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Objective data sheet
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA VDDD VCC Tstg Tamb Tj
[1] [2]
Parameter analog supply voltage digital supply voltage supply voltage difference storage temperature ambient temperature junction temperature
Conditions
[1] [2]
Min 2.85 1.65 -55 -40 -
Max 3.6 1.95 +125 +85 125
Unit V V V C C C
VDDA - VDDD
The supply voltage VDDA may have any value between -0.5 V and +7.0 V provided that the supply voltage differences VCC are respected. The supply voltage VDDD may have any value between -0.5 V and +5.0 V provided that the supply voltage differences VCC are respected.
8. Thermal characteristics
Table 4. Symbol Rth(j-a) Rth(j-c)
[1] [2]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions
[1] [1]
Typ 20.9[2]
Unit K/W K/W
In compliance with JEDEC test board, in free air. Value for 4 layers and 36 vias.
9. Static characteristics
Table 5. Characteristics Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C and CL = 5 pF. Min. and max. values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; Vi (INAP, INBP) - Vi (INAM, INBM) = -1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. Symbol Supplies VDDA VDDD IDDA IDDD Ptot analog supply voltage digital supply voltage analog supply current digital supply current total power dissipation fclk = 125 Msample/s; fi =70 MHz fclk = 125 Msample/s; fi = 70 MHz fclk = 125 Msample/s fclk = 105 Msample/s fclk = 80 Msample/s fclk = 65 Msample/s 2.85 1.65 3.0 1.8 343 150 1270 1150 995 885 3.4 3.6 V V mA mA mW mW mW mW Parameter Conditions Min Typ Max Unit
ADC1413D065_080_105_125_2
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Objective data sheet
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 5. Characteristics ...continued Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C and CL = 5 pF. Min. and max. values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; Vi (INAP, INBP) - Vi (INAM, INBM) = -1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. Symbol P Digital inputs Clock inputs: pins CLKP and CLKM, AC coupled LVPECL, LVDS and Sinewave modes compatible Vi(clk)dif differential clock input voltage input voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current Input capacitance Input current input resistance input capacitance common-mode input voltage input bandwidth differential input voltage common-mode output voltage common-mode output current peak-to-peak 0.2 0.8 V (p-p) Parameter power dissipation Conditions power-down mode standby mode Min Typ 30 200 Max Unit mW mW
LVCMOS mode VI VIL VIH IIL IIH VIL VIH IIL IIH CI II RI CI VI(cm) Bi VI(dif) VO(cm) IO(cm) 0.3VDDA -6 -30 0 0.7VDDA -10 -50 -5 0.9 1 0 0.66VDDD 4 15 5 1.5 600 0.5VDDA 0.7VDDA +6 +30 0.3VDDA VDDA +10 +50 +5 2 2 V V V A A V V A A pF A pF V MHz V (p-p) V A Logic Inputs: Power-down: pin CF 0 to 3, pin scrambler, Swing_0, Swing_1
Serial Peripheral Interface: pin CSB, SDIO, SCLK, pin DFS, pin DCS
Analog inputs: pins INAP and INAM, pins INBP and INBM
Voltage controlled regulator output: pin VCMA, VCMB
ADC1413D065_080_105_125_2
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Objective data sheet
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 5. Characteristics ...continued Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C and CL = 5 pF. Min. and max. values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; Vi (INAP, INBP) - Vi (INAM, INBM) = -1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. Symbol VVREF Parameter voltage on pin VREF Conditions output input Reference mode selection: pin SENSE VSENSE voltage on pin SENSE pin AGND; VVREF; VDDA V Min 0.5 Typ 0.5 to 1 Max 1 Unit V V Reference voltage input/output: pin VREF
Data outputs: CMLPA, CMLNA Output levels, VDDD = 1.8 V {Swing_2, Swing_1, Swing_0} = {0,0,0} VOL VOH LOW-level output voltage HIGH-level output voltage DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled Differential; input Differential; input -5 1.5 1.65 1.8 1.35 1.45 1.625 1.8 1.275 1.4 1.6 1.8 1.2 1.35 1.575 1.8 1.125 1.3 1.55 1.8 1.05 0.95 1.47 1 +5 V V V V V V V V V V V V V V V V V V V V V V LSB
Output levels, VDDD = 1.8 V. {Swing_2, Swing_1, Swing_0}= {0,0,1} VOL VOH LOW-level output voltage HIGH-level output voltage
Output levels, VDDD = 1.8 V {Swing_2, Swing_1, swing_0} = {0,1,0} VOL VOH LOW-level output voltage HIGH-level output voltage
Output levels, VDDD = 1.8 V {Swing_2, Swing_1, Swing_0} = {0,1,1} VOL VOH LOW-level output voltage HIGH-level output voltage
Output levels, VDDD = 1.8 V {Swing_2, Swing_1,Swing_0} = {1,0,0} VOL VOH LOW-level output voltage HIGH-level output voltage
Serial configuration: SYNC_P, SYNC_N VIL VIH Accuracy INL integral non-linearity LOW-level input voltage High-level input voltage
ADC1413D065_080_105_125_2
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Objective data sheet
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 5. Characteristics ...continued Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C and CL = 5 pF. Min. and max. values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; Vi (INAP, INBP) - Vi (INAM, INBM) = -1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. Symbol DNL Eoffset EG MG(CTC) Supply PSRR Power Supply Rejection Ratio 100 mV (p-p) on VDDA 35 dBc Parameter differential non-linearity offset error gain error channel-to-channel gain matching Conditions no missing codes guaranteed Min -1 Typ 0.5 2 0.5 Max +1 Unit LSB mV % FS %
10. Dynamic characteristics
Table 6. Characteristics Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C and CL = 5 pF. Min. and max. values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; Vi (INAP, INBP) - Vi (INAM, INBM) = -1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. Symbol Parameter Conditions ADC1413D065
Min Typ Max
ADC1413D080
Min Typ Max
ADC1413D105
Min Typ Max
ADC1413D12 5
Min Typ Max
Unit
Analog signal processing 2H second harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz 3H third harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz THD total harmonic distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz ENOB effective number of bits fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz Nth(RMS) RMS thermal noise 94 93 90 88 92 91 90 88 88 87 86 83 94 93 91 88 93 92 90 87 88 87 86 83 96 92 91 85 91 91 90 88 87 87 85 82 96 93 91 85 90 89 87 87 87 86 84 82 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Bits Bits Bits Bits tbd
11.9 11.7 11.6 11.6 tbd -
11.9 11.7 11.6 11.5 tbd -
11.8 11.7 11.6 11.5 tbd -
11.8 11.7 11.6 11.5 tbd -
ADC1413D065_080_105_125_2
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Objective data sheet
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 6. Characteristics ...continued Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C and CL = 5 pF. Min. and max. values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; Vi (INAP, INBP) - Vi (INAM, INBM) = -1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. Symbol Parameter Conditions ADC1413D065
Min Typ Max
ADC1413D080
Min Typ Max
ADC1413D105
Min Typ Max
ADC1413D12 5
Min Typ Max
Unit
SNR
signal-to-noise ratio
fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz
-
73.2 72.4 71.8 71.3 91 90 89 86 94 93 92 89 tbd -
-
73.1 72.3 71.8 71.2 91 90 89 86 94 93 92 89 tbd -
-
72.9 72.3 71.7 71.1 90 90 88 85 93 93 91 88 tbd -
-
72.5 72.2 71.6 71 90 89 87 85 93 92 90 88 tbd -
dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dB
SFDR
spurious-free dynamic range
fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz
IMD
intermodulation fi = 3 MHz distortion fi = 30 MHz fi = 70 MHz fi = 170 MHz
ct(ch)
crosstalk between channels
fi = 70 MHz
11. Clock and digital output timing
Table 7. Characteristics Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C and CL = 5 pF. Min. and max. values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) - VI (INAM, INBM) = -1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. Symbol Parameter Conditions ADC1413D065
Min Typ Max
ADC1413D080
Min Typ Max
ADC1413D105
Min Typ Max
ADC1413D125
Min Typ Max
Unit
Clock timing input: pins CLKP and CLKM fclk tlat(data) clk td(s) twake clock frequency data latency time clock duty cycle sampling delay time wake-up time DCS en DCS dis 20 17 30 45 50 50 0.8 tbd 65 20 70 55 60 17 30 45 50 50 0.8 tbd 80 20 70 55 60 17 30 45 50 50 0.8 tbd 105 60 20 70 55 17 30 45 50 50 0.8 tbd 125 Msps 20 70 55 clk/cy % % ns ns
11.1 Serial output timings
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions are:
ADC1413D065_080_105_125_2
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Objective data sheet
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
* 3.125 Gbps data rate * Tamb = 25 C * DC coupling with 2 different receiver common-mode voltages.
005aaa088
Fig 3. Eye diagram at 1 V receiver common mode
005aaa089
Fig 4. Eye diagram at 2 V receiver common mode
12. SPI timing
Table 8. Characteristics Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C and CL = 5 pF. Min. and max. values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; Vi (INAP, INBP) - Vi (INAM, INBM) = -1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. Symbol tw(SCLK) tw(SCLKH) Parameter SCLK pulse width SCLK pulse width HIGH Conditions Min 40 16 Typ Max Unit ns ns Serial Peripheral Interface timings
ADC1413D065_080_105_125_2
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Objective data sheet
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 8. Characteristics ...continued Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C and CL = 5 pF. Min. and max. values are across the full temperature range Tamb = -40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; Vi (INAP, INBP) - Vi (INAM, INBM) = -1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. Symbol tw(SCLKL) tsu Parameter SCLK pulse width LOW set-up time data to SCLKH CSB to SCLKH th hold time data to SCLKH CSB to SCLKH fclk(max) maximum clock frequency 2 2 25 ns ns MHz Conditions Min 16 5 Typ Max Unit ns ns
13. Application information
13.1 Analog inputs
13.1.1 Input stage description
The ADC1413D inputs can be configured as single-ended or differential (selected via SPI control bit DIFF/SE; see Table 20). Optimal performance is achieved using differential inputs with the common-mode input voltage, VI(cm), set to VDDA/2. The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 13.2 and Table 21 for further details). The equivalent circuit of the sample and hold input stage, including ESD protection and circuit and package parasitics, is shown in Figure 5.
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Package
ESD
Parasitics
Switch INAP INBP 1, 14
Ron = 14 4 pF
Sampling internal Capacitor clock
INAM INBM
2, 13
Ron = 14
Switch
4 pF
Sampling internal Capacitor clock
005aaa069
Fig 5.
Input sampling circuit
The sample phase HIGH, because of the NMOS transistors. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core.
13.1.2 Anti-kickback circuitry
Anti-kickback circuitry is needed to counteract the effects of charge injection generated by the sampling capacitance. This consists of an RC filter containing a resistor in series (typically 12 to 25 ) and a capacitor in parallel (typically 8 pF to 12 pF). The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time too much. The RC coupling is determined by the input frequency and should be selected so as not to affect the input bandwidth.
Table 9. 3 MHz 70 MHz 170 MHz RC coupling versus input frequency R 25 12 12 C 12 pF 8 pF 8 pF
Input frequency
13.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 6 would be suitable for a baseband application.
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
100 nF
Analog lnput
100 nF
ADT1-1WT
25
25
INAP INBP
12 pF
100 nF 100 nF
25
25
INAM INBM VCM
100 nF
100 nF
005aaa070
Fig 6.
Single transformer configuration
ADT1-1WT
100 nF 50
ADT1-1WT
50
12
INAP INBP
8.2 pF
Analog lnput
50
50
12
100 nF
INAM INBM VCM
100 nF
100 nF
005aaa071
Fig 7.
Dual transformer configuration
The configuration shown in Figure 7 is recommended for high frequency applications. In both cases, the choice of transformer will be a compromise between cost and performance.
13.2 System reference and power management
13.2.1 Internal/external reference
The ADC1413D has a stable and accurate built-in internal reference voltage. This reference voltage can be set internally, externally or programmed, in 1 dB steps between 0 dB and -6 dB, via SPI control bits INTREF (when bit INTREF_EN = 1; see Table 21). The equivalent reference circuit is shown in Figure 8.
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
REFT REFERENCE AMP REFB
VREF
BUFFER
BANDGAP REFERENCE
ADC CORE SENSE SELECTION LOGIC
005aaa072
Fig 8.
Reference equivalent schematic
Table 10 shows how to choose between the different internal/external modes:
Table 10. Mode Internal Internal External Internal, SPI mode Reference modes SPI Bit, "Internal reference" 0 0 0 1 SENSE pin GND VREF pin Full Scale, V (p-p)
330 pF capacitor 2 to GND 1
VREF pin = SENSE pin and 330 pF capacitor to GND VDDA
External voltage 1 to 2 from 0.5 V to 1 V 1 to 2
VREF pin = SENSE pin and 330 pF capacitor to GND
Figure 9, Figure 10, Figure 11 and Figure 12 indicate how to connect the SENSE and VREF pins.
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
VREF
REFT
VREF
REFT
330 pF
330 pF
SENSE
REFB
SENSE
REFB
005aaa100
005aaa074
Fig 9.
Internal reference, 2 V (p-p) full scale
Fig 10. Internal reference, 1 V (p-p) full scale
VREF
REFT V SPI SETTINGS int_Ref = 1, active Programmable_int_ref = XXX
VREF
0.1 F
REFT
330 pF
SENSE
REFB
SENSE
REFB
005aaa075
VCCA
005aaa076
Fig 11. Internal reference, SPI, 1 V (p-p) to 2 V (p-p) full scale
Fig 12. External reference, 1 V (p-p) to 2 V (p-p) full scale
13.2.2 Gain control
The gain is programmable between 0 dB to -6 dB in steps of 1 dB via the SPI (see Table 21). This makes it possible to improve the Spurious-Free Dynamic Range (SFDR) of the ADC1413D. The corresponding full scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in Table 11:
Table 11. 000 001 010 011 100 101 110 111 Reference SPI gain control Level 0 dB -1 dB -2 dB -3 dB -4 dB -5 dB -6 dB not used Full Scale, V (p-p) 2 1.78 1.59 1.42 1.26 1.12 1 x
Programmable_int_ref
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
13.2.3 Common-mode output voltage (VI(cm))
An 0.1 F filter capacitor should be connected between on the one hand the pins VCMA and VCMB and on the other hand ground to ensure a low-noise common-mode output voltage. When AC-coupled, these pins can be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point.
PACKAGE
ESD
PARASITICS COMMON MODE REFERENCE
1.5 V VCMA VCMB
0.1 F
ADC CORE
005aaa077
Fig 13. Reference equivalent schematic
13.2.4 Biasing
The common-mode output voltage, VO(cm), should be set externally to 1.5 V (typical).The common-mode input voltage, VI(cm), at the inputs to the sample and hold stage (pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal performance. Figure 14 illustrates how the SFDR and SNR characteristics vary with changes in the common-mode input voltage.
dB SFDR (x MHz)
SNR (x MHz)
0.9 V
2V
VI(cm) 005aaa052
Fig 14. SFDR and SNR performances versus common-mode voltage
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
13.3 Clock input
13.3.1 Drive modes
The ADC1413D can be driven differentially (SINE, LVPECL or LVDS) without the performance being affected by the choice of configuration. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor).
LVCMOS clock input
CLKP CLKM LVCMOS clock input
CLKP CLKM
005aaa078
Fig 15. LVCMOS single-ended clock input
CLKP Sine Clock lnput
Sine Clock lnput
CLKP
CLKM
CLKM
005aaa079
Fig 16. Sine differential clock input
CLKP LVDS Clock lnput
CLKM
005aaa080
Fig 17. LVDS differential clock input
13.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode voltage of the differential input stage is set via internal resistors of 5 k resistors.
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
PACKAGE
ESD
PARASITICS
CLKP
Vcm(clk) Sel_SE Sel_SE
5k
5k
CLKM
005aaa081
Fig 18. Equivalent input circuit
Single-ended or differential clock inputs can be selected via the SPI interface (see Table 20). If single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting SE_SEL accordingly, the unused pin should be connected to ground via a capacitor.
13.3.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by compensating the input clock signal duty cycle. When the duty cycle stabilizer is active (bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and 55 %.
Table 12. 0 1 Duty cycle stabilizer Description Duty cycle stabilizer disable Duty cycle stabilizer enable
DCS_enable SPI
13.4 Digital outputs
13.4.1 Serial output equivalent circuit
The JESD204A standard specify that in case of connecting the receiver and the transmitter in DC coupling, both of them need to be provided by the same supply.
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
VDDD
50
+
CMLP CMLN
100
RECEIVER
+
-
12 to 26 mA
AGND
005aaa082
Fig 19. CML output connection to the receiver in DC coupling
The output should be terminated when 100 (typical) has been reached at the receiver side.
VDDD
50
+
CMLP CMLN
10 nF 100
10 nF
RECEIVER
+
-
12 to 26 mA
005aaa083
Fig 20. CML output connection to the receiver in AC coupling
13.5 JESD204A serializer
13.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the JESD204A standard. This ensures signal integrity and guarantees the clock and the data recovery at the receiver side. The block is highly parameterized and can be configured in various ways depending on the sampling frequency and the number of lanes used.
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
M CONVERTERS
L LANES
N bits from Cr0 + CS bits for control
F octets TX transport layer
FRAME TO OCTETS
SCRAMBLER
ALIGNMENT CHARACTER GENERATOR
8b/10b
SER
LANE0
SYNC~
TX CONTROLLER
N bits from CrM-1 + CS bits for control
samples stream to lane stream mapping
F octets
FRAME TO OCTETS
SCRAMBLER
ALIGNMENT CHARACTER GENERATOR
8b/10b
SER
LANE-1
N' = N+CS S samples per frame cycle
CF: position of controls bits HD: frame boundary break Padding with Tails bits (TT) Lx(F) octets L octets
005aaa084
Mx(N'xS) bits
Fig 21. General overview of the JESD204A serializer
ADC_mode [1-0]
PRBS
11 N & CS
scramb_in_mode [1-0] lane_mode [1-0] SCR PRBS 01 '0' 8b/10b
DUMMY
14 + 1
10
14 + 1
N + CS
8
00
10
00
ADC_power down 01 14 + 1 00 bypass alignment disable_char_repl x1 PLL & DLL xF x 10F frame CLK char CLK bit CLK PRBS sync_request ADC1 14 + 1 00 '0' ADC_power down PRBS N & CS 01 SCR N + CS 8 00 8b/10b 10 01 11 FRAME ASSEMBLY FSM (f assy, char repl, ILA, test mode) '0/1' PRBS 10
lane_polarity SER
ADC0
11
swing [2-0]
'0/1'
10
SER
lane_polarity 00
DUMMY PRBS
14 + 1 10
14 + 1
lane_mode [1-0]
11
scramb_in_mode [1-0]
ADC_mode [1-0]
005aaa085
Fig 22. Detailed view of the JESD204A serializer with debug functionality
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
13.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Table 13. < -1 -1 -0.9998779 -0.9997559 -0.9996338 -0.9995117 .... -0.0002441 -0.0001221 0 +0.0001221 +0.0002441 .... +0.9995117 +0.9996338 +0.9997559 +0.9998779 +1 > +1 Output codes versus input voltage Offset binary 00 0000 0000 0000 00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0010 00 0000 0000 0011 00 0000 0000 0100 .... 01 1111 1111 1110 01 1111 1111 1111 10 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0010 .... 11 1111 1111 1011 11 1111 1111 1100 11 1111 1111 1101 11 1111 1111 1110 11 1111 1111 1111 11 1111 1111 1111 Two's complement 10 0000 0000 0000 10 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0010 10 0000 0000 0011 10 0000 0000 0100 .... 11 1111 1111 1110 11 1111 1111 1111 00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0010 .... 01 1111 1111 1011 01 1111 1111 1100 01 1111 1111 1101 01 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 OTR 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
INP-INM (V)
13.6 Serial Peripheral Interface (SPI)
13.6.1 Register description
The ADC1413D serial interface is a synchronous serial communications port allowing for easy interfacing with many industry microprocessors. It provides access to the registers that control the operation of the chip in both read and write modes. This interface is configured as a 3-wire type (SDIO as bidirectional pin). SCLK acts as the serial clock, and CSB acts as the serial chip select bar. Each read/write operation is sequenced by the CSB signal and enabled by a LOW level to to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte (see Table 14).
Table 14. Bit Description Instruction bytes for the SPI MSB 7 R/W[1] A7
[1]
ADC1413D065_080_105_125_2
LSB 6 W1 A6 5 W0 A5 4 A12 A4 3 A11 A3 2 A10 A2 1 A9 A1 0 A8 A0
R/W indicates whether a read or write transfer occurs after the instruction byte
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Read or Write mode access description Description Write mode operation Read mode operation
Table 15. R/W[1] 0 1
[1]
Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Table 16. W1 0 0 1 1
Number of bytes to be transferred W0 0 1 0 1 Number of bytes 1 byte transferred 2 bytes transferred 3 bytes transferred 4 or more bytes transferred
Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is incremented to access subsequent addresses. The steps involved in a data transfer are as follows: 1. The falling edge on CSB in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can be vary in length but will always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes):
CSB
SCLK
SDIO
R/W
W1
W0
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa086
Fig 23. Transfer diagram for 2 data bytes (3 wires mode)
13.6.2 Channel control
The two ADC channels can be configured at the same time or separately. By using the register "Channel index", the user can choose which ADC channel will receive the next SPI-instruction. By default the channel A and B will receive the same instructions.
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 17.
Register allocation map R/W Bit definition Bit 7 R/W R/W SW_ RST R/W R/W R/W R/W R/W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ADCB PD[1:0] Bit 0 ADCA Default Bin 1111 1111 0000 0000
Addr Register name Hex 0003 Channel index 0005 Reset and Operating modes 0006 Clock 0008 Vref 0011 Output data standard 0013 Offset 0014 Test pattern 1 0015 Test pattern 2 0016 Test pattern 3 JESD204A control 0801 Ser_Status 0802 Ser_Reset 0803 Ser_Cfg_Setup 0805 Ser_Control1
SE_SEL DIFF/SE LVDS/ CMOS INTREF_ EN OUTBUF
CLKDIV2_ DCS_EN 0000 SEL 000X 0000 0000 000X 0XXX 0000 0000
INTREF[2:0] DATA_FORMAT
DIG_OFFSET[5:0] TESTPAT_1[2:0]
0000 0000 0000 0000 0000 0000
R/W TESTPAT_2[13:6] R/W TESTPAT_3[5:0]
R
0
RESERVED[2:0] 0 0 0 0 0 0
0
0
POR_TST PLL_ 0000 INLOCK 0000 0 0 0000 0000 0000 ****[1] 0100 1000
R/W SW_ RST R/W 0 R/W 0
FSM_SW_ 0 RST CFG_SETUP[3:0]
TriState SYNC_ _CFG_ POL PAD 0 0
SYNC_ 1 SINGLE ENDED 0 0
RESERVED[2:0]
0806 Ser_Control2
R/W 0
0
SWAP_ SWAP_ 0000 LANE_1_2 ADC_0_ 00** 1 0000 01** 0000 0000 1111 1111
0808 Ser_Analog_Ctrl 0809 Ser_ScramblerA 080A Ser_ScramblerB 080B Ser_PRBS_Ctrl 0820 Cfg_0_DID 0821 Cfg_1_BID 0822 Cfg_3_SCR_L
R/W 0 R/W
0
0
0
0
SWING_SEL[2:0]
LSB_INIT[7:0]
R/W MSB_INIT[7:0] R/W 0 R/W*
[2]
0 DID[7:0] 0 0
0
0
0
0
PRBS_TYPE[1:0]
0000 0000 1110 1101
R/W* 0 R/W* SCR
0 0
0 0
BID[3:0] 0 0 0 L
0000 1010 *000 000*
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 17.
Register allocation map ...continued R/W Bit definition Bit 7 R/W* 0 R/W* 0 R/W* 0 R/W* 0 R 0 Bit 6 0 0 0 CS[0] 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 Bit 4 0 K[4:0] 0 0 NP[4:0] 0 0 LID[4:0] LID[4:0] 0 0 0 0 0 CF[1:0] S 0 0 0 N[2:0] 0 M Bit 3 0 Bit 2 F[2:0] Bit 1 Bit 0 Default Bin 0000 0*** 000* **** 0000 000* 0100 0*** 0000 1111 0000 0000 *000 0000 0001 1011 0001 1100 0000 0000 0000 0000 LANE_ LANE_ LANE_ POL CLK_POS PD _EDGE LANE_ LANE_ LANE_ POL CLK_POS PD _EDGE 0 0 0 0 0000 000* 0000 000*
Addr Register name Hex 0823 Cfg_4_F 0824 Cfg_5_K 0825 Cfg_6_M 0826 Cfg_7_CS_N 0827 Cfg_8_Np 0828 Cfg_9_S 0829 Cfg_10_HD_CF 082C Cfg_01_2_LID 082D Cfg_02_2_LID 084C Cfg01_13_FCHK 084D Cfg02_13_FCHK 0870 Lane01_0_Ctrl
R/W* 0 R/W* HD R/W* 0 R/W* 0 R R
FCHK[7:0] FCHK[7:0] SCR_ LANE_MODE[1:0] 0 IN_ MODE SCR_ LANE_MODE[1:0] 0 IN_ MODE 0 0 ADC_MODE[1:0] ADC_MODE[1:0] 0 0
R/W 0
0871 Lane02_0_Ctrl
R/W 0
0890 Adc01_0_Ctrl 0891 Adc02_0_Ctrl
R/W 0 R/W 0
ADC_PD 0000 000* ADC_PD 0000 000*
[1] [2]
an "*" in the Default column replaces a bit of which the value depends on the binary level of external pins (e.g. CFG[3:0], Swing[1:0], Scrambler). an "*" in the Access column means that this register is subject to control access conditions in Write mode.
13.6.3 Register description
Table 18. Bit 1 Register channel Index (address 0003h) Access R/W 0 1 0 ADCA R/W 0 1
ADC1413D065_080_105_125_2
Symbol ADCB
Value
Description ADCB will get the next SPI command: ADCB not selected ADCB selected ADCA will get the next SPI command: ADCA not selected ADCA selected
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 19. Bit 7
Register reset and Power-down mode (address 0005h) Access R/W 0 1 Value Description Reset digital part: no reset performs a reset of the digital part Power-down mode: 00 01 10 11 normal (power-up) full power-down sleep normal (power-up)
Symbol SW_RST
1 to 0
PD
R/W
Table 20. Bit 4
Register clock (address 0006h) Access R/W 0 1 Value Description Select SE clock input pin: Select CLKM input Select CLKP input Differential/single ended clock input select: 0 1 Fully differential Single-ended Select clock input divider by 2: 0 1 disable active Duty cycle stabilizer enable: 0 1 disable active
Symbol SE_SEL
3
DIFF/SE
R/W
1
CLKDIV2_SEL
R/W
0
DCS_EN
R/W
Table 21. Bit 3
Register Vref (address 0008h) Access R/W 0 1 Value Description Enable internal programmable VREF mode: disable active Programmable internal reference: 000 001 010 011 100 101 110 111 0 dB (FS=2 V) -1 dB (FS=1.78 V) -2 dB (FS=1.59 V) -3 dB (FS=1.42 V) -4 dB (FS=1.26 V) -5 dB (FS=1.12 V) -6 dB (FS=1 V) not used
Symbol INTREF_EN
2 to 0
INTREF
R/W
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 22. Dec +31 ... 0 ... -32 Table 23. Bit 2 to 0
Digital offset adjust Digital_Offset_Adjust[5:0] 011111 ... 000000 ... 100000 Register test pattern 1 (address 0014h) Access R/W 000 001 010 011 100 101 110 111 Value Description Digital test pattern: off mid-scale - FS + FS toggle `1111..1111'/'0000..0000' Custom test pattern, to be written in register 0015h and 0016h `010101...' `101010...' +31 LSB ... 0 ... -32 LSB
Register offset: (address 0013h)
Symbol TESTPAT_1
Table 24. Bit 13 to 6
Register test pattern 2 (address 0015h) Symbol TESTPAT_2 Access R/W Value Description Custom digital test pattern
Table 25. Bit 5 to 0
Register test pattern 3 (address 0016h) Access R/W Value Description Custom digital test pattern
Symbol TESTPAT_3
13.6.4 JESD204A digital control registers
Table 26. Bit 7 to 1 0 PLL_Inlock R 0 SER status (address 0801h) Access Value Description Not used Indicates status of PLL Symbol
Table 27. Bit 7 6 to 4 3 2 to 0
SER reset (address 0802h) Access R/W R/W Value 0 000 0 000 Description Initiates a software reset of the JEDEC204A unit Not used Initiates a software reset of the internal state machine of JEDEC204A unit Not used
(c) NXP B.V. 2009. All rights reserved.
Symbol SW_RST FSM_SW_RST -
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 28. Bit 7 to 4 3 to 0 -
SER cfg set-up (address 0803h) Access R R/W Value 0000 0000 (reset) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 to 1101 1110 1111 Description Not used Defines quick JESD204A configuration. These settings overrule the CFG_PAD configuration ADC0: ON; ADC1: ON; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9; M = 2; L = 2[1] ADC0: ON; ADC1: ON; Lane0: ON; Lane1: OFF; F = 4; HD = 0; K = 5; M = 2; L = 1[1] ADC0: ON; ADC1: ON; Lane0: OFF; Lane1: ON; F = 4; HD = 0; K = 5; M = 2; L = 1 swap line = 1[1] ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17; M = 1; L = 2[1] ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17; M = 1; L = 2; swap adc = 1[1] ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9; M = 1; L = 1[1] ADC0: ON; ADC1: OFF; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9; M = 1; L = 1; swap line = 1[1] ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9; M = 1; L = 1; swap adc = 1[1] ADC0: OFF; ADC1: ON; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9; M = 1; L = 1; swap adc = 1; swap line = 1[1] Reserved ADC0: OFF; ADC1: OFF; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9; M = 2; L = 2; loop alignment = 1[1] ADC0: OFF; ADC1: OFF; Lane0: OFF; Lane1: OFF; F = 2; HD = 0; K = 9; M = 2; L = 2 PD[1]
Symbol CFG_SETUP
[1]
F: number of byte per frame; HD: High density; K: number of frames per multi frame; M: number of converters; L: number of lanes
See the information about the JESD204A standard on the JEDEC web site.
Table 29. Bit 7 6 5 TRISTATE_CFG_PAD SYNC_POL SER control1 (address 0805h) Access R R/W R/W 0 (default) 1 4 SYNC_SINGLE_ENDED R/W 0 (default) 1 3 2 REV_SCR R 0 (default) 1
ADC1413D065_080_105_125_2
Symbol
Value 0 1 (default)
Description Not used CFG pads (3 to 0) are set to high-impedance Defines the sync signal polarity: Synchronization signal is active low Synchronization signal is active high Defines the input mode of the sync signal: Synchronization input mode is set in Differential mode Synchronization input mode is set in Single-ended mode Not used Enables swapping bits at the scrambler input LSB are swapped to MSB at the scrambler input
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 29. Bit 1
SER control1 (address 0805h) ...continued Access 0 (default) 1 LSB are swapped to MSB at the 8b/10b encoder input Enables swapping bits at the lane input (before serializer): 0 (default) 1 LSB are swapped to MSB at the lane input Value Description Enables swapping bits at the 8b/10b encoder input:
Symbol REV_ENCODER
0
REV_SERIAL
-
Table 30. Bit 7 to 2 1 -
SER control2 (address 0806h) Access R R/W 0 (default) 1 Outputs of the JESD204A unit are swapped. (Output0 is connected to Lane1, Output1 is connected to Lane0) Controls the JESD204A input multiplexer: 0 (default) 1 Inputs of the JESD204A unit are swapped. (ADC0 output is connected to Input1, ADC1 is connected to Input0) Value 000000 Description Not used Controls the JESD204A output multiplexer:
Symbol SWAP_LANE_1_2
0
SWAP_ADC_0_1
R/W
Table 31. Bit 7 to 3 2 to 0 -
SER analog ctrl (address 0808h) Access R R/W Value 0 000 Description Not used Defines the swing output for the lane pads
Symbol SWING_SEL
Table 32. Bit 7 6 to 0 -
SER scramblerA (address 0809h) Access R R/W Value 0 0000000 Description Not used Defines the initialization vector for the scrambler polynomial (Lower)
Symbol LSB_INIT
Table 33. Bit 7 to 0
SER scramblerB (address 080Ah) Access R/W Value Description 11111111 Defines the initialization vector for the scrambler polynomial (Upper)
Symbol UPP_VECT_INIT
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 34. Bit 7 to 2 1 to 0 -
SER PRBS Ctrl (address 080Bh) Access R R/W 00 (reset) 01 10 11 Value 000000 Description Not used Defines the type of Pseudo-Random Binary Sequence (PRBS) generator to be used: PRBS-7 PRBS-7 PRBS-23 PRBS-31
Symbol PRBS_TYPE
Table 35. Bit 7 to 0
Cfg_0_DID (address 0820h) Access R Value Description 11101101 Defines the device (= link) identification number
Symbol DID
Table 36. Bit 7 to 4 3 to 0 -
Cfg_1_BID (address 0821h) Access R R/W Value 0000 1010 Description Not used Defines the bank ID - extension to DID
Symbol BID
Table 37. Bit 7 6 to 1 0
Cfg_3_SCR_L (address 0822h) Access R/W R R/W Cfg_4_F (address 0823h) Access R R/W Cfg_5_K (address 0824h) Access R R/W Cfg_6_M (address 0825h) Access R R/W Value 0000000 0 Description Not used Defines the number of converters per device, minus 1 Value 000 00000 Description Not used Defines the number of frames per multiframe, minus 1 Value 00000 000 Description Not used Defines the number of octets per frame, minus 1 Value 0 000000 0 Description Scrambling enabled Not used Defines the number of lanes per converter device, minus 1
Symbol SCR L
Table 38. Bit 7 to 3 2 to 0 F
Symbol
Table 39. Bit 7 to 5 4 to 0 K
Symbol
Table 40. Bit 7 to 1 0 M
Symbol
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 41. Bit 7 6 5 to 4 3 to 0 CS N
Cfg_7_CS_N (address 0826h) Access R R/W R R/W Cfg_8_Np (address 0827h) Access R R/W Cfg_9_S (address 0828h) Access R R/W Value 0000000 0 Description Not used Defines number of samples per converter per frame cycle Value 000 00000 Description Not used Defines the total number of bits per sample, minus 1 Value 0 0 00 0000 Description Not used Defines the number of control bits per sample, minus 1 Not used Defines the converter resolution
Symbol
Table 42. Bit 7 to 5 4 to 0 NP
Symbol
Table 43. Bit 7 to 1 0 S
Symbol
Table 44. Bit 7 6 to 2 1 to 0 HD CF
Cfg_10_HD_CF (address 0829h) Access R/W R R/W Cfg01_2_LID (address 082Ch) Access R R/W Value 000 11011 Description Not used Defines lane1 identification number Value 0 00000 00 Description Defines high density format Not used Defines number of control words per frame clock cycle per link.
Symbol
Table 45. Bit 7 to 5 4 to 0 -
Symbol LID
Table 46. Bit 7 to 5 4 to 0 -
Cfg02_2_LID (address 082Dh) Access R R/W Value 000 11100 Description Not used Defines lane2 identification number
Symbol LID
Table 47. Bit 7 to 0
Cfg02_13_fchk (address 084Ch) Access R Value Description Checksum corresponds to the sum of all the link configuration parameters modulo 256 (as defined in JEDEC Standard No.204A) 00000000 Defines the checksum value for lane1
Symbol FCHK
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Rev. 02 -- 4 June 2009
31 of 38
NXP Semiconductors
ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 48. Bit 7 to 0
Cfg01_13_fchk (address 084Dh) Access R Value Description Checksum corresponds to the sum of all the link configuration parameters module 256 (as defined in JEDEC Standard No.204A) 00000000 Defines the checksum value for lane1
Symbol FCHK
Table 49. Bit 7 6 -
Lane01_0_ctrl (address 0870h) Access R R/W 0 (reset) 1 Value 0 Description Not used Defines the input type for scrambler and 8b/10b units: (Normal mode) = Input of the scrambler and 8b/10b units is the output of the frame assembly unit. Input of the scrambler and 8b/10b units is the PRSB generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_ctrl register) Defines output type of Lane output unit: 00 (reset) 01 10 11 Normal mode: Lane output is the 8b/10b output unit Constant mode: Lane output is set to a constant (0 x 0) Toggle mode: Lane output is toggling between 0 x 0 and 0 x 1 PRBS mode: Lane output is the PRSB generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_ctrl register) Not used Defines lane polarity: 0 1 Lane polarity is normal Lane polarity is inverted Defines lane clock polarity: 0 1 Lane clock provided to the serializer is active on positive edge Lane clock provided to the serializer is active on negative edge Lane power-down control: 0 1 Lane is in Power-down mode
Symbol SCR_IN_MODE
5 to 4
LANE_MODE
R/W
3 2
LANE_POL
R R/W
0
1
LANE_CLK_POS_EDGE R/W
0
Lane_PD
R/W
Table 50. Bit 7 6 -
Lane02_0_ctrl (address 0871h) Access R R/W 0 (reset) 1 Value 0 Description Not used Defines the input type for scrambler and 8b/10b units: (Normal mode) = Input of the scrambler and 8b/10b units is the output of the Frame Assembly unit. Input of the scrambler and 8b/10b units is the PRSB generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_ctrl register)
Symbol SCR_IN_MODE
ADC1413D065_080_105_125_2
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 -- 4 June 2009
32 of 38
NXP Semiconductors
ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 50. Bit 5 to 4
Lane02_0_ctrl (address 0871h) ...continued Access R/W 00 (reset) 01 10 11 Value Description Defines output type of lane output unit: Normal mode: Lane output is the 8b/10b output unit Constant mode: Lane output is set to a constant (0x0) Toggle mode: Lane output is toggling between 0x0 and 0x1 PRBS mode: Lane output is the PRSB generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_ctrl register) Not used Defines lane polarity: 0 1 Lane polarity is normal Lane polarity is inverted Defines lane clock polarity: 0 1 Lane clock provided to the serializer is active on positive edge Lane clock provided to the serializer is active on negative edge Lane power-down control: 0 1 Lane is in Power-down mode
Symbol LANE_MODE
3 2
LANE_POL
R R/W
0
1
LANE_CLK_POS_EDGE R/W
0
Lane_PD
R/W
Table 51. Bit 7 to 6 5 to 4 -
ADC01_0_ctrl (address 0890h) Access R R/W 00 (reset) 01 10 11 Value 00 Description Not used Defines input type of JESD204A unit: ADC output is connected to the JESD204A input Not used JESD204A input is fed with a dummy constant, set to: OTR = 1 and ADC[13:0] = "10011011101010" JESD204A is fed with a PRBS generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_ctrl register) Not used ADC power-down control: ADC is in Power-down mode
Symbol ADC_MODE
3 to 1 0
ADC_PD
R R/W
000 0 0 1
Table 52. Bit 7 to 6 5 to 4 -
ADC02_0_ctrl (address 0891h) Access R R/W Value 00 00 01 10 11 Description Not used ADC output is connected to the JESD204A input Not used JESD204A input is fed with a dummy constant, set to: OTR = 1 and ADC[13:0] = "10011011101010" JESD204A is fed with a PRBS generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_ctrl register) Not used
(c) NXP B.V. 2009. All rights reserved.
Symbol ADC_MODE
00 (reset) Defines input type of JESD204A unit
3 to 1
-
R
000
ADC1413D065_080_105_125_2
Objective data sheet
Rev. 02 -- 4 June 2009
33 of 38
NXP Semiconductors
ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 52. Bit 0
ADC02_0_ctrl (address 0891h) ...continued Access R/W 0 1 ADC is in Power-down mode Value Description ADC power-down control:
Symbol ADC_PD
13.6.5 Serial interface timings
The Figure 24 shows the SPI timings:
tsu CS
th
tsu
tw(SCLKL) tw(SCLK) tw(SCLKH)
th
SCLK
SDIO
R/W
W1
W0
A12
A11
D2
D1
D0
005aaa065
Fig 24. SPI timings
The timing specification link to Figure 24 is described in the Table 8.
ADC1413D065_080_105_125_2
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 -- 4 June 2009
34 of 38
NXP Semiconductors
ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
14. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm
SOT684-7
D
B
A
terminal 1 index area
E
A
A1 c
detail X
e1 e L 15 14 1/2 e b 28 29 e v w CAB C y1 C
C y
Eh 1/2 e
e2
1 terminal 1 index area 56 Dh 43
42 X
0 Dimensions Unit mm A(1) A1 b c 0.2 D(1) 8.1 8.0 7.9 Dh 5.95 5.80 5.65 E(1) 8.1 8.0 7.9 Eh 6.55 6.40 6.25 e 0.5
2.5 scale e1 6.5 e2 6.5
5 mm
L 0.5 0.4 0.3
v 0.1
w
y
y1 0.1
max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18
0.05 0.05
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT684-7 References IEC --JEDEC MO-220 JEITA --European projection
sot684-7_po
Issue date 08-11-19 09-03-04
Fig 25. Package outline SOT684-1 (HVQFN56)
ADC1413D065_080_105_125_2 (c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 -- 4 June 2009
35 of 38
NXP Semiconductors
ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
15. Revision history
Table 53. Revision history Release date Data sheet status Objective data sheet Objective data sheet Change notice Supersedes ADC1413D065_080_105_125_1 Document ID
ADC1413D065_080_105_125_2 20090604 Modifications:
*
Values in Table 7 have been updated.
ADC1413D065_080_105_125_1 20090528
ADC1413D065_080_105_125_2
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 -- 4 June 2009
36 of 38
NXP Semiconductors
ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
ADC1413D065_080_105_125_2
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 -- 4 June 2009
37 of 38
NXP Semiconductors
ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
18. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 11.1 12 13 13.1 13.1.1 13.1.2 13.1.3 13.2 13.2.1 13.2.2 13.2.3 13.2.4 13.3 13.3.1 13.3.2 13.3.3 13.4 13.4.1 13.5 13.5.1 13.5.2 13.6 13.6.1 13.6.2 13.6.3 13.6.4 13.6.5 14 15 16 16.1 16.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Clock and digital output timing . . . . . . . . . . . 10 Serial output timings . . . . . . . . . . . . . . . . . . . 10 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 12 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12 Input stage description . . . . . . . . . . . . . . . . . . 12 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 13 Transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 System reference and power management . . 14 Internal/external reference . . . . . . . . . . . . . . . 14 Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Common-mode output voltage (VI(cm)) . . . . . . 17 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Equivalent input circuit . . . . . . . . . . . . . . . . . . 18 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 19 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial output equivalent circuit . . . . . . . . . . . . 19 JESD204A serializer. . . . . . . . . . . . . . . . . . . . 20 Digital JESD204A formatter . . . . . . . . . . . . . . 20 ADC core output codes versus input voltage . 22 Serial Peripheral Interface (SPI) . . . . . . . . . . . 22 Register description . . . . . . . . . . . . . . . . . . . . 22 Channel control. . . . . . . . . . . . . . . . . . . . . . . . 23 Register description . . . . . . . . . . . . . . . . . . . . 25 JESD204A digital control registers . . . . . . . . . 27 Serial interface timings . . . . . . . . . . . . . . . . . . 34 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 36 Legal information. . . . . . . . . . . . . . . . . . . . . . . 37 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 16.3 16.4 17 18 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 38
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 June 2009 Document identifier: ADC1413D065_080_105_125_2

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